Smart Sensor
Dr. H. Johansson and Prof. L. Wanhammar
Project Description
Reduction of receiver complexity is becoming increasingly important in
order to minimize receiver size and cost for various radar and communication
systems. In digital beam forming antennas, where a large number of
parallel heterodyne receiver channels is needed, the size and cost is of
great importance. The main objective of this project is to find efficient
and low cost receiver implementation strategies, well adopted for digital
beamforming antennas used in adaptive radar systems. Frequency tuneable MMIC-filters in combination with integrated image
rejection mixers, high speed ADC's and fast digital filters can open the
door for the on-chip microwave-to-digital converting receiver. The activities are divided in three main parts: MMIC components, high speed
ADC's and digital filters.
The project is financed by The Swedish Foundation for Strategic Research is a research cooperation between
Linköping University (Department of Physics and Measurement Technology
(IFM) and Department of Electrical Engineering (ISY)), and The Defence
Research Establishment (FOA) in Linköping, in cooperation with Ericsson,
Saab and CelsiusTech. For more information about the project, see
RadarOnChip.
Digital Filters
The digital filters used in a digital beamforming antenna system consists of a Hilbert filter to
split the signal into I and Q channels, a digital down converter (DDC) for
decimation of the sample frequency, and, finally, an equalizer. It should
be stressed that the sample rate in this part of the system is very high
and the three latter parts represent a very high computational work load
and therefore require a delicate co-optimization of algorithm,
architecture, logic, and CMOS circuitry. One task in this project is to
evaluate and select the best among different filter structures. Other
important aims is to find methods for reducing the design time without
reducing the efficiency of the implementation, get practical experience of
system-on-a-chip issues such as global clocking and mixed-mode circuit
design.
Publications
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Ohlsson H., Johansson H. and Wanhammar L. "Implementation of a Combined
High-Speed Interpolation and Decimation Wave Digital Filter", In
proceedings of the International Conference on Electronics, Cicuits and Systems,
Paphos, Cyprus, Sep. 5-8, 1999, pp. 721-724.
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Ohlsson H., Johansson H. and Wanhammar L. "Design of a Digital Down
Converter Using High Speed Digital Filters", In proceedings of the Symposium on Gigahertz
Electronics, Gothenburg, Sweden, Mar. 13-14, 2000, pp. 309-312.
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H. Ohlsson, H. Johansson, and L. Wanhammar "Implementation of a combined
interpolator and decimator for an OFDM system demonstrator," IEEE NorChip
Conf 2000, Turku, Finland, 6-7 Nov, 2000, pp. 47-52.
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H. Ohlsson and L. Wanhammar, " Implementation of bit-parallel
lattice wave digital filters," Swedish System-on-Chip
Conf., SSoCC'01, Arild, Sweden,
March 20-21, 2001.
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O. Gustafsson, H. Ohlsson, and L. Wanhammar, " Minimum-adder integer
multipliers using carry-save adders," IEEE Int. Symp.
Circuits Syst., Sydney, Australia, May 6-9, 2001, pp. 709-713.
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H. Ohlsson, O. Gustafsson, and L. Wanhammar, " Arithmetic
transformations for increased maximal sample rate of
bit-parallel bireciprocal lattice wave digital filters," IEEE Int. Symp. Circuits Syst., Sydney, Australia,
May 6-9, 2001, pp. 825-828.
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H. Ohlsson, O. Gustafsson, H. Johansson and L. Wanhammar, "
Implementation of lattice wave digital filters with increased
maximal sample rate,"
IEEE Int. Conf. Elec. Circuits Syst., Malta,
Sep 6-9, 2001.
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