LOW-POWER FFT PROCESSORS

Weidong Li and Prof. Lars Wanhammar

---

Background

Many communication systems based on OFDM are recently suggested in both wireless and cable applications, like wideband radio terminals, DAB, HDTV and xDSL. The FFT/IFFT are two key DSP functional blocks in these systems. In fact, the FFT/IFFT are most frequently used functions in DSP.
High performance FFT/IFFT processors are difficult to design since it requires high memory access and high computation craft. Moreover, the higher power density, which is bieffect of the VLSI technology advance, has been one of the main design constraints. Hence the efficient design of low-power FFT/IFFT processors is vital.

Objective

• To develop efficient design and implementation techniques for algorithm-specific FFT processor cores with given throughput and dynamic rage requirements.
• To develop efficient CMOS implementations of critical blocks, e.g., complex multipliers, radix-r butter-flies, and specialized memory structures.
• To develop techniques to optimize data memory word length throughout the processor in order to minimize the power consumption.
• To develop efficient FFT processor architectures in order to minimize the power consumption.
• demonstrate the efficiency of our approach by designing a few test circuit for some real-world applica-tions, e.g., wideband radio modems and VDSL.

Research

The research is concerntrated on the design methology with respects from the system/architecture to the implementation.

• System and architecture
  The system requirement has main impact on the realization. The research focus on the relationship between system and hardware requirement with the aspect of power consumption. New design procedures are being developed to minimize the power consumption in combination of efficient architectures.
• Implementation
  New efficient CMOS implementation of basic building blocks are being developed for low voltage operations.

Members

Currently the following persons are involved in this project.

• Weidong Li, Ph.D. student, e-mail weidongl@isy.liu.se, phone +46 13 281721.
• Lars Wanhammar, Prof., Dr., e-mail larsw@isy.liu.se, phone +46 13 281344.

Project funding

This project is funded by the INTELECT programme, which is financed by the Foundation for Strategic Research, SSF.

Publications

• W. Li and L. Wanhammar,"VHDL Code Generator for a Complex Multiplier,"
  RVK, Karlskrona, Sweden, June, 1999.
  
  
• W. Li and L. Wanhammar,"A Complex Multiplier Using 'Overturned-Stairs' Adder Tree,"
  ICECS, Paphos, Cyprus, Sept.,1999.
  
  
• W. Li, Y. Ma and L. Wanhammar,"Word Length Estimation for Memory Efficient Pipeline FFT/IFFT Processors,"
  ICSPAT, Orlando, Florida, USA, Nov., 1999.
  
  
• W. Li and L. Wanhammar,"A Pipeline FFT Processor,"
  SiPS, Taipei, China, Oct., 1999.
  
  
• W. Li and L. Wanhammar,"Efficient Radix-4 and Radix-8 Butterfly Elements,"
  Norchip, Oslo, Norway, Nov., 1999.
  
  
• W. Li and L. Wanhammar,"Low Power FFT Procesors,"
  Swedish System-on-Chip Conf., SSoCC'01, Arild, Sweden, March 20-21, 2001.
  
  
• W. Li, S. Zhuang, and L. Wanhammar,"A Pipeline Complex Multiplier,"
  ISIC, Singapore, Sep., 2001.