Advanced A/D and D/A CMOS Converters
- High speed data conversion using hybrid filter banks
Dr. P. Löwenborg, Dr. H. Johansson, and Prof. L. Wanhammar
Introduction
Analog-to-digital converters (ADCs) [1] and digital-to-analog
converters (DACs) [2] are required in almost all signal processing and
communication systems. They are often the most critical components,
i.e., they tend to determine the overall system performance. Hence, it
is important to determine their performance limitations and develop
improved realizations. In this project we focus on a particular type
of potentially high-performance analog-to-digital conversion
technique, where two or more ADCs are operated in parallel in a so
called hybrid filter bank. The resulting A/D converter is called a
hybrid filter bank based A/D converter (HFB ADC). In principle, HFBs
can be used for D/A conversion as well, but focus has in this project
almost exclusively been put on the ADC problem.
There are several existing analog-to-digital conversion techniques,
which can be grouped into categories such as flash converters,
subranging converters, successive-approximation converters,
integrating converters, and oversampling sigma-delta converters. The
ADC performance is mainly described in terms of the sampling rate, the
resolution which is given by the number of quantization levels, and
the dynamic range which determines the effective resolution under the
influence of errors in the converter.
One ADC scheme that achieves high sampling rate is time-interleaved ADCs (TI ADCs) [3], for which a number of converters, belonging to the categories above, work in parallel at a lower sampling rate. This enables an overall high sampling rate. The main drawback, however, is the limited dynamic range that is due to channel mismatch errors.
The design of integrated analog circuitry, for example conventional data converters, has come to a stage where the performance of the implemented circuit is mostly limited by the errors introduced in fabrication (if a good design has been made) and the design effort is merely concentrated on minimizing the effect of such fabrication-induced errors. However, the minimization of the actual fabrication errors is sometimes not enough to meet the increasing requirements. The invention of new schemes and structures for data conversion is therefore necessary. Two such schemes for high-speed and high-resolution ADCs are the HFB ADC [4], [5] and TI ADCs with mismatch error correction [6] - [8]. The work that has been performed during this project has been designated to these two schemes.
Filter Bank-Based A/D Converters
In filter bank-based converters, a discrete-time or analog analysis filter bank is used together with a digital synthesis filter bank. Such filter banks are commonly denoted as hybrid filter banks (HFBs). The term hybrid is used since discrete-time or analog filters are used together with digital filters, forming a HFB system. The TI ADC scheme can in fact be seen as a special case of the HFB ADC scheme. Hybrid filter banks are divided into two different classes, hybrid discrete-time/digital filter banks (DT HFB) and hybrid analog/digital filter banks (CT HFB).
Hybrid Discrete-Time/Digital Filter Bank-Based ADCs
In the following it is assumed that the input signal is strictly
bandlimited to . In this case, the Nyquist criterion for sampling with
an effective sampling frequency of 1/T without aliasing is met. Hence,
it is possible to, in principle, completely eliminate aliasing in the
filter bank by properly designing the analysis and synthesis filter
banks. Hence, the actual aliasing in the overall ADC will be
determined by the anti-aliasing filter that must precede the filter
bank. The aliasing will then be identical to that of a single
conventional ADC that uses the same anti-aliasing filter.
The principle of an M-channel DT HFB ADC is illustrated in Fig. 1. The
analog input signal xa(t) is sampled at the input of a discrete-time
analysis filter bank with filters Hk(z).
Figure 1. Principle of an M-channel hybrid discrete-time/digital filter bank-based ADC.
The filter banks considered here are either uniform-band that divide
the input signal frequency band into M equally wide frequency bands or
octave-band that successively divide for example the low frequency
band into smaller and smaller frequency ranges. The signals in each
channel can then be downsampled by a factor corresponding to the
signal bandwidth without any loss of information. The signals are then
quantized before they are upsampled by a factor of M and filtered
through a digital synthesis filter bank with filters Gk(z). The output
signal y(n) is obtained by adding the corresponding output
signals.
An advantage of the DT HFB ADCs is that techniques for realizing the required discrete-time filters, e.g., switched-capacitor filters and charge-coupled devices, can be implemented with higher accuracy than what usually can be achieved by integrated continuous-time filters. For example the accuracy of SC-filters is mostly determined by capacitance ratios, which are more accurate than absolute capacitance values, which are used in other techniques. In the DT HFB ADCs, channel mismatch errors in terms of static time-skew errors will not occur, since only one sampling operation is performed. The filter banks will, further, attenuate aliasing caused by channel mismatch errors in terms of static gain errors.
The main disadvantage with the DT HFB ADC is that the sampling of the
input signal, which is inherent in discrete-time filter banks, needs
to be performed with a sampling rate corresponding to the full signal
bandwidth. Note that SC-filters, which are common discrete-time
filters, have a sampling circuit at their inputs that converts a
continuous-time signal to a discrete-time signal. The effect of any
errors that are introduced during sampling will not be attenuated by
the filter banks since the effect of the combined filter banks
corresponds to a delay or an allpass function. The DT HFB ADC type is
suitable for medium sampling rates, but with higher requirements on
the dynamic range.
Hybrid Analog/Digital Filter Bank-Based ADCs
The principle of a CT HFB ADC is illustrated in Fig. 2. The input
signal xa(t) is here directly fed into an analog analysis filter bank
with filters Hk(s). These are designed to be uniform-band and
therefore, each channel can be sampled at one Mth of the sampling
frequency of the overall ADC. The sampling takes place at the output
of Hk(s) and therefore static gain and time-skew errors that occur in
the sampling process are attenuated by a combination of the filters of
the analysis and synthesis filter banks, as will be discussed later.
Figure 2. Principle of an M-channel hybrid analog/digital filter bank based-ADC.
The sampling of the signal in the lowpass channel is a lowpass
sampling process. In the remaining channels, bandpass signals are
sampled. With practical filters, thus having finite stopband
attenuation and non-zero transition bandwidths, a certain amount of
aliasing will inevitably occur during sampling in all channels. This
aliasing, however, is controlled in the filter design and is identical
to the aliasing introduced due to practical anti-aliasing filters that
must precede any ADC. After sampling and quantization each signal is
upsampled before filtered through the digital synthesis filter bank
with filters Gk(z). Each converter works with a reduced sampling
rate.
The analog filters are also more suitable for high bandwidth signals
than discrete-time filters. Therefore, the CT HFB ADC is potentially
more suitable for high-speed analog-to-digital conversion. Channel
mismatch errors in terms of both gain- and time-skew errors will
occur, but the introduced aliasing will be attenuated by the filters.
TI ADCs with Error Correction
In TI ADCs, channel mismatch errors will be present in practical
implementations. The aliasing that is introduced is the main error
source and limits the effective resolution to about 8 to 10 bits.
Using filter HFB ADCs this aliasing is attenuated by the filters.
The channel mismatch errors can also be mitigated by using error
correction techniques. In Fig. 3, M TI ADCs with channel mismatch
error correction is shown. The input signal is in each channel sampled
at , where Dtk are static time-skew errors. This is, for each channel
in Fig. 3, modelled using delays of tk, k = 0, 1, ..., N-1 followed by
simultaneous sampling at t = mMT. After upsampling, the signals are
processed using a reconstruction system constituting a filter bank of
adjustable fractional delay filters Ek(z), followed by a lowpass
filter F(z). Using such a reconstruction system, the output signal
y(n) can be reconstructed to contain the same frequency contents as
xa(nT) in the frequency region of interest, using an oversampling by a
factor less than or equal to two.
Figure 3. Principle of M TI ADCs with channel mismatch error correction using a synthesis filter bank.
Project Objectives
The work that has been done during this project has been directed towards the following obejctives:
HFB ADC analysis
In order to properly design and understand HFB ADCs a thorough analysis must be made. Important issues are frequency response, including distortion and aliasing, quantization noise, requirements on the filters given certain requirements on the effective resolution, sensitivity analysis, reduction of channel mismatch-induced aliasing by using filter banks etc.
Hybrid filter bank design
When designing the filter banks, a so called distortion function and
several aliasing terms have to be optimized to meet some prescribed
characteristics. For the DT HFBs, the design problem is in fact the
same as for purely digital maximally decimated filter banks. Whereas
it is possible for digital filter banks (and therefore also DT HFBs)
to achieve perfect reconstruction (PR), it appears to be impossible
for CT HFBs if the analog filter bank is assumed to be realized using
only lumped elements. If transmission lines are used as components it
would be possible to find CT HFBs with PR. The design of the
analog/digital type is a more challenging task. The frequency
responses of the analog filters, which are rational functions in jw,
need to be matched with the frequency responses of the digital
filters, which are rational functions of ejwT, in order to
simultaneously minimize both distortion and aliasing.
In order to minimize the hardware cost of the analog parts we propose to use design procedures where the analog part is designed independently of the digital filters. By first designing the analog filters the complexity of these can be minimized, given that the frequency selective requirements due to the dynamic performance requirements of the HFB ADC is met. Then, with a fixed analysis filter bank, the digital filters can be designed in order to meet the requirements on distortion and aliasing.
Due to the possibility to minimize the complexity of the analog or discrete-time filters and the reduction of the number of design parameters, all of the HFB structures proposed in this work are asymmetric in the sense that the analysis and synthesis filter banks have different complexities.
Realization aspects
Suitable structures for the analog filter banks as well as suitable filter bank classes for DT and CT HFBs should be investigated. Further, reliable and practical design procedures for those filter bank classes should be developed.
Results
Results of Analysis
- Expressions for the frequency responses of uniform band maximally
decimated HFBs and HFBs with rational interpolation factors has been
derived and analyzed. Even though these frequency responses are
central to the filter bank design and further analysis, few
publications on hybrid analog/digital filter banks (CT HFBs) utilize
the correct frequency response expression.
- The quantization noise in multirate HFB ADCs which is fundamental to
the ADC performance has been investigated. This has earlier been done
only for single-rate filter bank ADCs, where all converters are
operated at the higher sampling rate. In this project we have
investigated the quantization noise also for the multirate case and
compared the resulting signal-to-quantization noise-ratio with
time-interleaved ADCs and a single ADC. It has been shown that using a
correct scaling policy, the SNR of a HFB ADC is identical to that of a
single ADC for wideband input signals.
- Further, the spurious free dynamic range improvement by using HFB ADCs
compared with time-interleaved ADCs (TI ADCs), has been investigated
in the presence of static gain- and time-skew errors. Expressions for
the spurious free dynamic range has been derived. This sets the
specification of the filters used in the filter bank given the
requirements on the spurious free dynamic range of the ADC.
- The effect of wideband noise at the output of the analog or
discrete-time filter bank has been investigated.
- The sensitivity of the distortion and aliasing functions has been investigated and it has been shown that the aliasing terms are most sensitive in the transition regions of the filters while less being less sensitive for passband frequencies.
Results of Filter Bank Design and Realization
- During the project, low-sensitivity filter structures, suitable for
use as reference structures for multi-band analog or discrete-time
filters, have been proposed. These filter bank structures make use of
diplexers, connected in a tree-structure. The design of such
structures has been studied.
- First-order sensitivity expressions of the frequency responses with
respect to filter component values have been derived for
diplexer-based reference structures and it has been shown that the
sensitivity is about an order of magnitude less than for doubly
resistively terminated ladder networks, realizing the same transfer
functions, the latter being known to have very low sensitivity of the
magnitude function with respect to the component values.
- A number of asymmetric filter bank structures has, further, been
proposed and corresponding design principles have been developed. The
proposed CT HFBs approximate perfect reconstruction or perfect
magnitude reconstruction. The design of the proposed filter banks is
performed by first optimizing the analog analysis filters and then,
with the analysis filters fixed, optimizing the digital synthesis
filters. This design procedure makes it possible to obtain analysis
filters of very low order and complexity. The overall complexity is
also low. Both FIR and IIR filters are used in the synthesis filter
bank. Also, two-channel CT HFBs with rational interpolation factors
has been proposed. Such structures are advantageous from a sensitivity
point of view.
- Asymmetric two-channel and M-channel hybrid discrete-time/digital
filter bank (DT HFB) classes have also been proposed as well as
suitable design procedures. The proposed asymmetric DT HFB structures
can also be used as purely digital filter banks and are as such
suitable for applications where low-complexity is desired in certain
parts of the system, like battery-powered communications equipment.
The proposed filter banks have analysis filters that are half-band IIR
filters whereas the synthesis filters are FIR filters. The complexity
of the analysis filter bank is then very low whereas that of the
synthesis filter bank is higher. The proposed two-channel DT HFBs are
near perfect reconstruction filter banks. They have magnitude
distortion, but no phase distortion. Further, the aliasing can be made
either exactly zero or approximately zero. The proposed M-channel
filter bank extensions, being tree-structures using two-channel filter
banks as elementary building blocks, also have magnitude distortion,
but no phase distortion. Further, the aliasing terms are exactly zero
for a uniform-band filter bank case whereas they approximate zero in a
octave-band case.
- A technique for correcting nonuniformly sampled and bandlimited
signals using a filter bank consisting of adjustable fractional delay
filters has been proposed. The proposed technique can be applied to
the correction of channel mismatch errors in TI ADCs. The proposed
synthesis system is attractive from an implementation point of view,
because the required filters need not be redesigned when the gain- and
time-skew errors are changed. It suffices to only adjust a few
multiplier coefficient values. These can be adjusted directly
according to measured values of the mismatch errors or be adaptively
adjusted using some adaptation scheme. Also the error correction can
be performed as good as desired by increasing the hardware complexity
of the reconstruction system. A requirement for these advantageous
properties is the need for a slight oversampling (oversampling factor
less than 2).
- The design and realization of adjustable fractional delay filters,
suitable to the proposed reconstruction scheme, has been studied.
References
[1] Tan N., "Oversampling A/D converters and current-Mode techniques," Linköping studies in science and technology, diss. No. 360, Linköping University, Sweden, 1994.
[2] Wikner J. J., "Studies on CMOS digital-to-analog converters," Linköping studies in science and technology, diss. No. 667, Linköping University, Sweden, April 2001.
[3] Black W. C. and Hodges D. A., "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. SC-15, no. 6, pp. 1022-1029, Dec. 1980.
[4] Löwenborg P., Johansson H., and Wanhammar L., "A class of two-channel approximately perfect reconstruction hybrid analog/digital filter banks," in Proc. IEEE Int. Symp. Circuits Syst., Geneva, Switzerland, May 28-31, 2000.
[5] Löwenborg P., Johansson H., and Wanhammar L., "A class of two-channel IIR/FIR filter banks," in Proc. X European Signal Processing Conf., Tampere, Finland, Sept. 5-8, 2000.
[6] Johansson H. and Löwenborg P., "Reconstruction of nonuniformly sampled bandlimited signals by means of digital fractional delay filters," in Proc. IEEE Trans. Signal Processing. Vol. 50, No. 11, Nov. 2002.
[7] Eldar Y. C. and Oppenheim A. V., "Filterbank reconstruction of bandlimited signals from nonuniform and generalized samples," IEEE Trans. Signal Processing, vol. 48, no. 10, pp. 2864-2875, Oct. 2000.
[8] Jin H. and Lee K. F., "A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADC's," IEEE Trans. Circuits Syst. II, vol. 47, no. 7, pp. 603-613, July 2000.
Research status
Outcome
Doctoral Thesis
Members
The following persons are involved in this project.
- Per
Löwenborg, Dr.,
e-mail perl@isy.liu.se, phone +46 13 281676.
- Håkan Johansson, Dr.,
e-mail hakanj@isy.liu.se, phone +46 13 281347.
- Lars Wanhammar, Prof., Dr.,
e-mail larsw@isy.liu.se, phone +46 13 281344.
Project Funding
This project was funded through the
INTELECT
programme, which is financed by the
Foundation for Strategic Research, SSF.
For information and questions regarding this web site,
please contact Per Löwenborg, perl@isy.liu.se
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