DSP System Design
M.Sc. H. Ohlsson, Dr. H. Johansson, Dr. K. Palmkvist, and Prof.
The aim of this project is to develop efficient design methods and adapt
necessary tools for low-power and low-cost DSP systems with given throughput
requirements. Typically the average throughput is fixed, but burst of computations
may be required.
To be efficient the approach will focus on a limited and well defined
set of DSP systems that have some critical characteristics in common. That
is, we do not believe that one single approach will be efficient and suitable
for all types of applications. Instead we will focus on high-volume, low
cost integrated DSP systems/components. Typical examples can be found in
future communication systems both on radio and copper wires. These systems
will typically have high or very high throughput and at the same time operate
on a stringent power budget, which means that power consumption is a major
design issue at all design levels. Further, the development time will be
very short since these systems are consumer products. Hence, the development
technique is also of major importance.
We intend to develop an approach based on the fact that most of the
of the target systems can be described on a high level of abstraction by
a data-flow description. This description lend itself to an isomorphic
implementation approach with globally asynchronous communication between
the components while the components are locally synchronous. This means
that the components can be optimized with respect to functionality, throughput,
and power consumption. Thus, an efficient and robust asynchronous communication
scheme with corresponding implementation must be developed.
Digital filters and in particular digital filters for decimation and interpolation
are important components in most DSP systems. These types of filters are
required in most A/D and D/A converters. Currently high-speed decimation
and interpolation filter consume about the same power as an A/D converter.
Hence, more efficient implementations are required in order to allow a
larger part of the power budget to the analog circuitry which can not take
advantages of reduced geometries. During the last few years we have proposed
a large number of new filter structures that aim at these applications.
However, the new structures must be evaluated by comparison of their performance
in terms of design effort, maximal speed, and power consumption. Further
an efficient design route must be developed since there are very large
number of possible variations.
Asynchronous DSP Systems
This part involve the design of the overall system. This is indeed a very
large topic and will require several Ph.D. students. We will in the beginning
focus on the design and implementation of an asynchronous interface. Important
issues here are of course robustness, but also speed and power consumption,
voltage level converters, etc. Future work will focus on, for example,
performance and power consumption estimates and testing issues.
Currently the following persons are involved in this project.
Henrik Ohlsson, M.Sc.,
e-mail firstname.lastname@example.org, phone
+46 13 284059.
Ph.D., e-mail email@example.com,
phone +46 13 281347.
Kent Palmkvist, Ph.D.,
e-mail firstname.lastname@example.org, phone +46
Lars Wanhammar, Ph.D.,
Prof., e-mail email@example.com, phone
+46 13 281344.
This project is funded by the INTELECT
programme, which is financed by the Foundation for Strategic Research, SSF.
H. Ohlsson, H. Johansson, and L. Wanhammar. "Implementation of
a combined high-speed interpolation and decimation wave digital filter,
in Proc. IEEE Int. Conf. Electronics Circuits Syst., Pafos, Cyprus, Sept.
5-8, 1999, pp. 721-724.
H. Ohlsson, H. Johansson, and L. Wanhammar, " Design of a digital down
converter using high speed digital filters," Symposium on Gigahertz Electronics,
GHz2000, Gothenburg, Sweden, March 13-14, 2000, pp. 309-312.
H. Ohlsson and L. Wanhammar, " Implementation of a digital beamformer
in an FPGA using distributed arithmetic," IEEE Nordic Signal Processing
Symposium, Norsig2000, Kolmården, Sweden, June 13-15, 2000,
H. Ohlsson, H. Johansson, and L. Wanhammar "Implementation of a combined
interpolator and decimator for an OFDM system demonstrator," IEEE NorChip
Conf 2000, Turku, Finland, 6-7 Nov, 2000, pp. 47-52.
H. Ohlsson and L. Wanhammar, " Implementation of bit-parallel
lattice wave digital filters," Swedish System-on-Chip
Conf., SSoCC'01, Arild, Sweden,
March 20-21, 2001.
O. Gustafsson, H. Ohlsson, and L. Wanhammar, " Minimum-adder integer
multipliers using carry-save adders," IEEE Int. Symp.
Circuits Syst., Sydney, Australia, May 6-9, 2001, pp. 709-713.
H. Ohlsson, O. Gustafsson, and L. Wanhammar, " Arithmetic
transformations for increased maximal sample rate of
bit-parallel bireciprocal lattice wave digital filters," IEEE Int. Symp. Circuits Syst., Sydney, Australia,
May 6-9, 2001, pp. 825-828.
H. Ohlsson, O. Gustafsson, H. Johansson and L. Wanhammar, "
Implementation of lattice wave digital filters with increased
maximal sample rate,"
IEEE Int. Conf. Elec. Circuits Syst., Malta,
Sep 6-9, 2001.