Responsible for this page: J Jacob Wikner , email@example.com
Page last update: 2012-02-13
RF-DACs, mixer DACs, all-digital DACs, sigma-delta modulators, direct-to-antenna, digital/analog co-design, all-digital
- project background and industrial motive
We present a research project where we focus on high-speed mixed-signal circuits and algorithms for integration in digital-to-analog converters.
For the next-generation radio telecommunication systems we require very high linearity and not only limiting ourselves to some 60 or 70 dB. (60 to 70 dB is the typical range that is sufficient to cover the most wide-spread telecommunication standards, such as GSM, LTE, WCDMA, WLAN, etc.) However, there are other application areas, such as, for example, next-generation radar that put even higher requirements on linearity: up to 100 dB in a wide frequency band.
For both applications, the sampling speed should be as high as possible. For software-defined radio (SDR) we also require that the system can tune over a fairly large frequency range (such that it is flexible and can adopt to several different standards), but the signal band itself can be rather small.
The main purpose of this project is to shorten the analog signal chain by reducing the number of analog components. The result of this operation is that the digital sampling speed, analog updating speed, as well as the requirement on linearity and frequency selectivity increases quite dramatically.
The DAC is often considered to be a less complex component and "easier" to design than the ADC, which is found in the receive path. We have however seen in our previous research that a lot of effort still can be put on the DAC to improve performance: we have for example contributed to so called dynamic element matching techniques (DEM) that effectively improve the linearity of high-speed DACs. We have also looked at other ways to more or less perform blind linearization of the DAC. These results have been published within the framework of previous projects at Electronics Systems.
Another scope of the project is to implement our devices in standard, digital CMOS processes that are available in large volumes and that are intended for e.g. the consumer market. This is in some sense contradictory to the usage in applications like radar, but it becomes a more interesting research challenge, where we do not rely on exotic materials or special expensive equipment to solve our problem. Perhaps more importantly, it gives us access to all the main-stream digital design tools available for these processes. Further on, we can integrate our solutions with larger digital cores.We want to develop a design methodology for as well as implementation of devices where high-speed digital sigma-delta modulation, time-interleaving of several units, and on-chip mixers are combined into one component. This enables us to co-optimize the components and design for optimum performance. As an outcome of the project we define a design strategy for high-speed DACs suitable for wideband applications with demanding requirements on linearity.
We foresee that this project will result in advances both on circuit and system level. Even though our main philosophy is a top-down strategy, and that much of the advances can be done on an algorithmic level, we know we have to spend quite some time looking at the smallest unit elements as well as the capability of the transistors in the modern CMOS processes. This includes the fabrication and measurement of chips.
- a description of the research group where the project is conductedThe research on high-speed D/A converters, as suggested in this project, is being performed at the Electronics Systems group, at the Department of Electrical Engineering (ISY), Linköping University.
The group leader, Dr. J Jacob Wikner, is currently conducting research on different types of mixed-signal integrated circuits (high-speed, low-power) and has several publications in the area of D/A and A/D converters for communication applications. He has a 10-year industrial experience where for example D/A converters for WCDMA, A/VDSL, WLAN and AFEs for video applications have been developed in process nodes down to below 40 nm. The mixed-signal integrated circuits have been developed to be placed into large systems on chip with focus on low-voltage technologies.
Naturally, people have been studying variants of the proposed research field at throughout the years (ourselves included). The updating frequency and the linearity has been steadily increasing. Currently the fastest, high-resolution DACs are still in the sub-GHz region or close above.
There are plenty of academic publications demonstrating high-speed D/A converters, but as stated, still in the sub-GHz region, and still somewhat modest linearity, and publications demonstrating results in the high GHz region uses more exotic processes, such as SiGe or SOI principles. Typically you find from all reported results (and theory) that the there is a relationship between resolution (i.e. linearity) and frequency: with higher frequency or bandwidth, the linearity decreases.
Luschas, et al., published some very interesting research results in 2004: "Radio Frequency Digital-to-Analog Converter". It is rather straight-forward as such: a sigma-delta modulator (SDM) is used to reduce the number of analog components in the RF DAC. Dynamic element matching (DEM) is used to scramble data and decorrelate static errors from the signal to further reduce nonlinearity. The sigma-delta modulator is an effective way to spectrally shape quantization errors such that a DAC with less analog contents can be used.
The results they present are elegant in the way that they have successfully implemented a mixing switching scheme to the DAC. They have been able to apply a carefully designed oscillator signal to the internal elements of the DAC such that they achieve a mixed signal at the output of the DAC.
What Luschas, et al., have achieved is to further shape the oscillating signal such that the spectral weighting of the DAC output is not attenuated that much at certain frequency bands above the sample frequency. Instead the lobes at higher frequency are (relatively) amplified, such that a local maximum is achieved at approximately twice the sample frequency, equal to the oscillating frequency. They report 75-dBc linearity in a 17.5-MHz band centered at 942 MHz. The technique is promising, but it is not wide-band enough and linearity must be increased.
Another way to increase frequency is to use time-interleaved converters consisting of severalDACs connected in parallel by summation of the outputs. The DACs operate at time shifted clocks, but same frequency. By carefully generating the time shifts with high accuracy PLL and DLL, we could for example let all the DACs operate at say 1 GHz, but with a 120-degree phase shift between each other (if three in parallel), thus outputting data at 3-GHz in total. The overall signal transfer function will be (undesirably) weighted where a pair of complex zeros are introduced in the frequency domain. Thereby the spectrum will be attenuated accordingly and certain frequency bands become distorted. However, if we are able to control the positions of these zeros, and/or keep our signal out of those bands, we still quite likely have a competitive solution to reach high speed conversion.
Optionally, one could have mixers at the outputs of the DACs rather than adders to avoid the zeros in the signal band. The mixers could however be integrated with the DACs on the same chip using special quadrature switching schemes.
Italian researchers have in 2009 proposed "Delta-Sigma Time-Interleaved Current Steering DAC with Dynamic Elements Matchingâ which is quite similar to the approach we are going to explore further. The recent date of this work gives us high confidence in and credibility to our research proposal. Similarly to this, from 2008, there are published results on time-interleaved, sigma-delta DACs, even though the measured and simulated results are somewhat moderate, the work shows fresh and promising ideas within the field. From these references, we can see that a large effort is put on the digital domain rather than the analog which is what we also are striving for with this proposal.
For a DAC, there is normally a relationship between resolution and frequency. With higher frequencies, the linearity decreases. In some sense, there is not much you can do about the slope of the curve. What one can do, though, to generically improve linearity is to move the upper frequency break-point by advances in technology and clever design. This upper frequency break-point is partly given by the so called transition-frequency, , of the transistor. (For frequencies below , the transistors of the process still yield a gain higher than one.) There are however other parameters that play a role too, and we want to explore ways to find the optimum values for the application. By knowing these limits we also know what barriers we cannot breach.
The Nyquist-rate converter is designed to use the entire available signal band from 0 to (i.e., up to Nyquist). Quite often this is an overdesign in many applications, since our bandwidth is actually quite often quite narrow banded.
There are two flavors of interpolating DACs: analog and digital interpolation. On the digital side, we apply digital multi-rate interpolators at the input of the DAC such that the update frequency is increased and signal can be located at higher frequencies through filtering. The advantage is that we can feed the DAC with a lower frequency input thus relaxing the interface to the circuit.
Sigma-delta modulators are attractive in many ways: they truncate the word length of the digital input word to the DAC and the error introduced by this operation is spectrally shaped to out-of-band frequencies. By filtering out this quantization noise which is outside the signal band we land at the original resolution within the band. They are also attractive since all operations are (unlike for ADCs) done in the digital domain. However, it is also highly nonlinear and has high-gain in the feedback loop making it hard to analyze and stabilize.
Sigma-delta DACs require a fairly high oversampling ratio between the sample frequency and signal bandwidth such that the added quantization noise can be moved far enough out-of-band and then filtered out with low complexity filters. If we for a moment neglect the complexity of the analog filter, the reduction in number of analog components using a sigma delta modulator is enormous. For example, if we have a 16-bit converter, we need components in a Nyquist-rate converter. By allowing ourselves a certain amount of oversampling we can now trade frequency against analog complexity. For example by allowing an oversampling of 16 times and apply a modulator with a third-order transfer function, we can reduce the number of components to approximately , i.e. 1000 times less components. With less analog complexity the design becomes simpler, more regular and accurate, even though the analog accuracy requirements are the same.
With a lower number of analog components in the design we can design for high-speed and apply dynamic element matching (DEM) techniques. These techniques use randomization to cancel out signal-dependent components and transforming this energy into noise. We have previously invented methods that can be applied to spectrally shape the error energy such that it falls out of band and does not degrade the signal-to-noise ratio in a small signal band  and we will continue this path.
It should be mentioned that for example digital pre-distortion (DPD) required to linearize the PA will need a bandwidth a couple of times wider than the signal band for proper cancellation of harmonics. To not destroy the properties of the DPD we cannot narrow down our bandwidth through the DAC too much. Researchers at MIT have however developed wideband digital sigma-delta modulators for high-speed applications with global feedback paths and still reached for example 200 MHz bandwidth at 5.25 GHz.
- long term vision of the project
In our research we want to explore and define new, high-speed sigma delta architectures that take these properties into account and how they can be used in a time-interleaved, parallel fashion to achieve a higher total updating speed with maintained linearity. Then we apply improved, high-speed DEM techniques together with analog DAC elements that are carefully designed for high frequencies following fundamental limits derived within the scope of the project.
Due to the high fabrication costs of state-of-the-art CMOS processes, we mainly focus on the algorithmic and simulator levels in this project. As project marches along, there will probably be options available to send test structures to fabrication on so called multi-project wafers (MPW) or similar student projects.
A limited number of physical ASIC implementations throughout project has the impliciation that we will rely less on empirical data - at least in the first half of the project - and plan to use an FPGA platform to evaluate some of the results together with a software platform as reference design.
- list of publications related to the project
- just a list of some external references
Authors: J Jacob Wikner, M Reza Sadeghifar, Nadeem Afzal
Please navigate to the ES' home page for more contact information.