Design and implementation of communication systems using the GALS approach

Background

Design of communication Systems-on-Chip (SoC) using deep submicron CMOS processes poses some new problems due to the increased system complexity and integration. A major problem is the slow, or at least inadequate, increase in design efficiency that has been observed for several decades. In fact, the design efficiency and testing schemes do not allow the potential of modern CMOS processes to be fully utilized.

In this project we address this issue using a divide and conquer technique that is applied at several levels of abstraction, e.g., system partitioning and hardware resource structure, and adopt a communication centered system view. Furthermore, we adopt a design process based on the successive development of a sequence of systems models with increasing details. The actual design phase is preceded by a problem understanding phase.

This approach support partitioning of design tasks on several teams and alleviate several design tasks. For example, chips containing whole systems will be large and/or operate at very high clock frequencies. Problems due to large power consumption and clock skew will therefore become significant and will increase with the increasing interconnection RC delay due to the scaling of the CMOS technology. Further, significant problems that consume large design efforts are due to the use of several clock domains, i.e., the operation and communication between different units must synchronized. Reuse of old designs and IP blocks is thereby significantly hampered.

We therefore adopt a global asynchronous communication scheme for the whole communication system. This can efficiently be implemented using an asynchronous wrapper for each local synchronous module (GALS), which allows the designer to focus on the design of the modules using traditional methods, without concern of synchronization issues.

Project

The aim is to develop efficient design methods and tools based on the Globally Asynchronous, Locally Synchronous (GALS) approach for implementation of communication systems, e.g., WLAN. With GALS, the system is partitioned into smaller synchronous modules, where each module use synchronous clocking scheme internally and communication between modules uses a well defined robust asynchronous communication protocol.

Since the synchronous modules are isolated from all other modules, different power supply voltage and clock speed can be used which also can be changed at runtime. Of special interest are aspects such as: design/development cost, ease of reuse of available blocks and IP blocks in heterogeneous architectures, and performance issues such as power consumption and chip area.

A set of associated asynchronous communication circuits for GALS systems will be developed and applied in several test systems or subsystems, e.g., WLAN, digital filters, and DCT/FFT processors.

Publications