The Device Sizing Tool

The device sizing tool is used to determine a set of design parameters so that the circuit performance meet the requirements. This may include minimizing or maximizing one or several performance measures.

Our design tool requires a small amount of human interaction. The inputs to the design tool are a circuit netlist, performance specification, and a technology. The netlist are entered using the standard interface in, e.g., the Cadence design systems schematic editor. An overview of the design tool is shown in the figure below.

The sizing tool uses an equation-based design approach, which means that the circuit performance is evaluated using symbolic equations rather than simulations. These symbolic equations are automatically generated from the netlist. The setup time for a medium size circuit (about 20 devices) is short, less than 10 minutes.

The sizing is performed by the use of a library of efficient optimization methods including both local and global algorithms. Throughout the sizing process the cost function evaluator penalizes poor solutions and drives the optimizer toward circuits meeting the performance requirements. At the end of the optimization, a sized circuit meting the specification is available. The optimization time is typically below one hour for medium size circuits.

Key features

The equation-based approach has the benefits of fast evaluation of the performance measures. This allows a thorough investigation of the design space to obtain circuit with good performance within reasonable time.

Automated generation of equations for performance measures enables short setup times and error-free equations for the performance measures when designinng a new circuit. It also enables the use of the same high-complexity device models as are used SPICE-like simulators.

High-accuracy device models are a key to estimate the performance obtained for a manufactured chip. Our tool uses the same device models as state-of-the-art circuit simulators. The device models are easily exchanged to facilitate fast migration between manufacturing processes.

Starting point independency means that a good initial design is not required to obtain circuits meeting the performance requirements. This reduces the preparatory work that has to be carried out. It also enables the use of less experienced designers to perform analog design.

Optimization algorithm. Several optimization algorithms are implemented in the tool to enable short design times and good results. The tool also supports distribution of optimization tasks onto a cluster of workstations which further reduces the design time.

Yield Enhancement is important to obtain robustness against variations due to manufacturing biases, temperature changes, and power supply variations. In order to increase robustness our tool uses yield enhancement techniques as an integral part of the design path.

Related design cases

A yield enhanced two stage operational transconductance amplifier

Related thesis works

Implementation of the EKV transistor model (PDF)
Extending the optimization-based device sizing program to handle multipliers (PDF)
From 0.35 μm to 70 nm - What will happen? (in Swedish) (PDF)
Extending the device sizing tool to design current conveyors (in Swedish) (PDF)

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