Parasitic Feedback

The purpose of the feedback tool is to compensate for parasitic devices introduced in the layout step. At the schematic level, only the parasitics originating from the devices are modeled since no information about the length and width of the interconnect wires are available. However, the interconnect parasitics may cause significant shifts in the circuit performance and must be taken into account in the circuit sizing. The major problem is that the correction of the performance shift requires adjustment of the device sizes, which in turn, will affect the layout and its parasitics.

In theory, this could be solved by performing simultaneously sizing and layout generation. However, in practice this would required that the layout generation step has to be performed for each set of devices sizes visited during the device sizing. Today, this is not feasible from a time perspective. Instead, we use a parasitic feedback loop to take into account and compensate for the performance shifts. This method is outlined in the figure below.

Initially, the device sizing is performed without any interconnect parasitics. These device sizes are used to generate a circuit layout from which the parasitics are extracted using a parasitics extraction tool. The parasitics are then included in the new netlist which is used to regenerate all equations required to evaluate the performance. If the specification is met, with the parasitics taken into account, the tool terminates the optimization. However, if the performance is not maintained, the parasitic feedback procedure is initiated.

The feedback initiates a new device sizing procedure in the previous solution, but with the extracted parasitics included. Hence, the device sizing tool is instructed to adjust the design parameters to meet the specification. The parasitic loads remain constant during this procedure.

The updated device sizes will cause changes in the layout; hence, a new layout must be generated. Here the previous layout is used as an initial starting point for this search. That is, only minor changes to the layout will be performed. The parasitic extraction tool is then used on this new layout.

This feedback procedure is repeated until the influence of parasitics on the performance is insignificant. Experimental results show that the parasitic feedback loop converges if the changes to both layout and devices sizes are made small by initiating the optimization with the previous solution. The final circuit is guaranteed to meet the performance requirements under the influence of layout induced parasitics.

Related design cases

Parasitic Feedback - Design Example

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