Responsible for this page: Lars Wanhammar , firstname.lastname@example.org
Page last update: 2008-05-08
The Layout Tool
In the layout step the circuit is mapped to its physical implementation. The devices are laid out and interconnected with wires. Traditionally, the layout step is time-consuming and might require the attention of the designer for several weeks. Here an overview of our vision for the layout generation tool is given. Some parts are already completed while others still remain.
The layout generation tool consists of an optimization-based place and route algorithm. The place and route parts are divided into two separate tasks, which are performed in a sequence. An overview of the tool is given in the figure below.
The layout generation tool uses a library of predefined devices. The number and complexity of the devices are kept low; a typical device in the device library is a single transistor or a matched transistor pair. This reduces the overhead when migrating form one process technology to the next. Each device has a number of properties that may be changed in order to change the appearence of each block, e.g., the width of a transistor.
The layout database is used to keep track on all objects in the design. It updates the design for each new set of design parameters generated by the placement and routing algorithms.
The cost evaluation consists of several modules that operate on the layout in order to determine its fitness. Modules to compute, e.g., overlap, aspect ratio, area, symmetry, or performance degradation may be used to facilitate a good layout.
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