Responsible for this page: Lars Wanhammar , firstname.lastname@example.org
Page last update: 2008-05-08
The Synthesis Tool
The objective of the synthesis tool is to increase the design efficiency when analog intergraded circuits are designed. By efficiency we here mean improved performance, reduced design time, and increased robustness compared to a manual design approach.
The focuses are on the time consuming device sizing and layout parts. However, the tool also supports compensation for layout induced parasitics and extensive design space exploration enabling comparison between circuit topologies and process technologies.
The principle design flow used within the tool is shown in the figure above. The input to the design tool is a circuit specification, containing the performance requirements and device matching, and a circuit topology, i.e., a circuit netlist. This is fed to the device sizing tool which determines the device sizes in order to meet the performance requirements.
This step is followed by the layout generation which transforms the circuit netlist into a physical description. In the layout step, the interconnect wires introduce parasitic loads in the circuit. These loads often degrade the performance of the circuit. Hence, such effects must be taken into account in the design process.
In the tool, the influence of the parasitics is compensated for by a feedback loop involving repeated device sizing and layout generation steps. By utilizing this iterative process, the layout will meet the specification with these parasitics taken into account.
The tool also supports design space exploration in order to compare several topologies for a certain specification. It may also be used to determine how, e.g., the area or power consumption will change if one or several performance requirements are changed. Using design space exploration allows better utilization of the process technology and helps the designer to make good trade-offs.