Responsible for this page: Oscar Gustafsson , oscarg@isy.liu.se
Page last update: 2008-05-08

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COMPUTER ARITHMETIC ALGORITHMS


Recommended for: Graduate students in computer science and electrical engineering.

Goals: Provide basic knowledge in computer arithmetic algorithms.
Organization: Lectures, exercises, and a minor design projects.
Literature: I. Koren, Computer Arithmetic Algorithms, A. K. Peters, Natick, MA, 2002.

Lectures

DateTimeRoomSubjectChapters
12/513-15NollställetRadix-based number systems1, 2
17/513-15NollställetFloating-point numbers4
10/613-15NollställetAddition5
8/910-12NollställetMultiplication3, 6
19/915-17NollställetDivision3, 7, 8
28/910-12NollställetElementary functions9
5/1010-12NollställetLogarithmic and residue number systems10, 11

Hand-in problems

Set 1
  • 1.1, 1.3, 1.9, 2.1, 2.8, 2.13
  • 4.1, 4.13
  • 5.1, 5.13, 5.20

    To be presented: 13-15 15/9 in Nollstället

    Set 2
  • 3.1, 3.4, 3.12
  • 6.3, 6.4, 6.20
  • 7.2, 7.8, 8.2, 8.8
  • 9.1, 10.2, 11.2

    To be presented: 13-15 13/10 in Nollstället

    Projects

    Student(s)SubjectPresentation timeReport
    Erik B. & Erik S.Fast minimum signed digit encoding26/10 10-11 in Nollstället[PDF]
    BehzadLogical effort for compressors24/1 10-11 in Nollstället[PDF]
    Andreas & PerHigh performance FPGA based floating point arithmetics31/5 10-11 in Nollstället[PDF]
    AntonData representation in LDPC decoders16/11 13-15 in Nollstället
    KennyFunction approximation for logarithmic number systems16/11 13-15 in Nollstället
    Anders & Eric T.DivisionTBD
    MattiasSine and cosine computationTBD
    JonasAsynchronous arithmeticTBD
    Johan & DiTBDTBD

    Outcomes

  • E. Backenius, E. Säll, and O. Gustafsson, "Bidirectional conversion to minimum signed-digit representation," IEEE Int. Symp. Circuits Syst., Kos Island, Greece, May 21-24, 2006.
  • A. Blad and O. Gustafsson, "Energy-efficient data representation in LDPC decoders," IET Electronics Letters, vol. 42, no. 18, pp. 1051-1052, 31 Aug. 2006.
  • K. Johansson, O. Gustafsson, and L. Wanhammar, "Conversion and addition in logarithmic number systems using a sum of bit-products," IEEE Norchip Conf., Linköping, Sweden, Nov. 20-21, 2006.
  • P. Karlström, A. Ehliar, and D. Liu, "High performance, low latency FPGA based floating point adder and multiplier units in a Virtex 4," IEEE Norchip Conf., Linköping, Sweden, Nov. 20-21, 2006.
    Teacher: Oscar Gustafsson
    Examination: Hand-ins plus implementation and presentation of small project
    Credits: 4 points


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    Last updated: 2008-05-08

    Responsible for this page:
    Oscar Gustafsson

    Org.nr: 202100-3096
    VAT nr: SE202100-309601
    Plusgiro: 18 34 15-9

    Electronics Systems
    Linköpings universitet
    581 83 LINKÖPING
    Tel: 013-28 10 00
    Fax: 013-13 92 82