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# Comparison of Three Operational Transconductance Amplifiers

To illustrate the design space exploration tool, a design example that evaluates three operational transconductance amplifiers (OTAs) to be used as buffers in an 8-bit sample-and-hold circuit with a 20-MHz sample frequency are given.

Although the tool handles fully differential circuits, we choose to illustrate the concept with single-ended circuits.

The circuit topologies for the three OTAs are shown in Fig. 1a (two-stage), Fig. 1b (folded-cascode), and Fig. 1c (current-mirror).

Fig. 1. The schematic of the two-stage (a), folded-cascode (b), and current-mirror (c) OTAs.

In Table 1 the performance specification for the OTAs is compiled. For sake of simplicity, no distortion or small-signal time-domain properties are included in the cost function, although the tool handles these as well.

Performance metrics Specification Unit
Unity-gain frequnecy > 100 MHz
Power supply voltage 3.3 V
PSRR > 70 dB
CMRR > 70 dB
Input range [1.0, 2.0] V
Output range [1.0, 2.0] V
DC gain > 70 dB
Slew rate > 100 V/μs
Phase margin > 60 degrees
Power consumption < 5.0 mW
Eq. output noise @ 1kHz< 320 μV/sqrt(Hz)

Table 1. The performance specification of the OTAs.

Since automatic derivation of expressions for slew rate has not yet been implemented they have been manually specified. For the OTAs, approximate expressions for the slew rate are essentially the supply current Id over the compensation Cc and/or load capacitance CL according to

SRts = min{Id3/Cc, Id5/(CL+Cc)},
SRfc = Id2a/(CL+Cc), and
SRcm = 2*Id7a/(CL+Cc).

for the two-stage, folded-cascode, and current-mirror OTA, respectively. Further, the currents through the transistors are computed at their operation points.

The area of the circuits are estimated by the width time the length of the transistors, resistors, and compensation capacitor. The area required for the routing and the substrate contacts are not included.

### Optimization setup

The biasing of the amplifiers is performed using external current mirrors and proper biasing schemes and is not part of the optimization problem. For the RC stabilization network two optimization parameters are used. In order to decrease the number of optimization variables the length of each transistor is fixed to twice the minimum size, i.e., 0.7 μm. Hence, only the width of each transistor is considered as an optimization parameter. Further, transistors sharing the same index, i.e., M1a and M1b, in Fig. 1a to Fig. 1c are assumed to be matched. A single optimization parameter is therefore used for the width of these transistors. In addition to the design parameters, the tool assigns additional optimization parameters for all electrical nodes in the circuit. The input voltages of the amplifiers are fixed to 1.5 V in all three cases. This leads to 13 optimization parameters for the two-stage OTA, 19 for the folded-cascode OTA, and 24 for the current-mirror OTA.

In order to generate symmetrical circuits, the ratio is set to unity for all matched transistors. It should though be pointed out that the circuit area and the power consumption of the current-mirror OTA can be decreased by using different currents in the left-most and right-most branches, by letting the mirror ratio between M3b and M4b be unity and the ratio between M6b and M6a (M7b and M7a) be equal to the ratio between M3a and M4a (M2a and M5a).

The design space is limited by constraining the design parameters within a range of acceptable values. The transistor widths are therefore limited to be in the range of 20 to 1000 μm. The size of the compensation network is constrained by allowing a capacitor with values in the range of 0.5 pF to 1 nF while the resistor should be in the range of 1 ohms to 1 Mohms. Further, all transistors are constrained to operate in the saturation region.

Due to the nonlinear nature of the optimization problem, several different starting points are required in order to find good solutions. The initial values of the optimization parameters are therefore randomly chosen between their upper and lower bounds. The node voltages are initially selected between the positive and negative power supply voltage.

# Optimization Results

In the following, the optimization results for the OTAs shown in Fig. 1 are presented. The optimization tool is directed to generate circuits that meet the specification in Table 1. The tool can simultaneously sweep several performance metrics in order to fully explore the design space. However, the graphs presented are two-dimensional cuts in this space. These are generated by sweeping the value of a performance metric, e.g., the power supply voltage, while minimizing, e.g., the power consumption.

In the graphs the performance metric being swept is placed on the x-axis while the metric being minimized/maximized is on the y-axis. Each point in the graphs represents the best of several solutions (local minima). For the examined topologies there exist several solutions with about the same cost, typically 90 % of the solutions, i.e., local minima, are within 10 % of the best solution.

The time required to generate the circuit parameters used for compiling the information in each of the graphs below is a few hours on a cluster of workstations.

For the circuits examined, the average time required to find one solution is about 3 minutes for the two-stage, 6 minutes the folded-cascode, and 8 minutes for the current-mirror OTA using a single workstation (Intel PentiumTM 4, 2.6 GHz). Hence, the approximate form of the presented curves can be generated in short time with low requirements on computer power.

The curves presented are based on results taken directly from the circuit optimizer, only a limited number of the solutions have been validated in the SpectreTM circuit simulator. These solutions show, however, an excellent agreement with the optimizer results due to the use of the same high accuracy transistor models (BSIM3v3) both in the optimization tool and in the SpectreTM simulator. Furthermore, special care has been taken in order to assure that the presented results are not affected by the setup and formulation of the optimization problem. For example, the impact of different relative weights of the performance metrics have been examined. Several different choices of weights have proven to yield the same results as the ones presented here.

### Impact of scaling the power supply voltage

In Fig. 2 the power consumption for the three amplifiers are shown as a function of the power supply voltage. The voltage has been decreased from 3.3 V until the circuit fails to meet the specification. The circuit area has not been constrained.

Fig. 2. The power consumption vs. the power supply voltage for the three amplifiers.

The graph shows the trade-offs between the power consumption and the power supply voltage for the circuit topologies. At 3.3 V, the current mirror OTA has the lowest power consumption, however, when lowering the power supply voltage below 2.8 V the two-stage amplifier is instead the best as far as the power consumption is concerned.

The graph also shows the range of power supply voltages for which the circuits meet the specification. The lower limit is set by the input and/or output swing of the amplifiers. Further, as the power supply voltage decreases from 3.3 V the power consumption also decreases linearly (constant power supply current) for the two-stage and the folded-cascode OTA. This is due to the slew rate limitation.

The minimum circuit areas required to meet the circuit specification as a function of the power supply voltage are shown in Fig.3.

Fig. 3. The circuit area as a function of the power supply voltage for the three different amplifiers. An extra curve for the two-stage OTA where the maximum power consumption is constrained to be within 0.1 mW of the minimum power consumption shown in Fig. 2.

For the two-stage amplifier two curves are plotted. In the lower-most curve no constraints on power consumption is applied, in the other the maximum power consumption is constrained to be within 0.1 mW from the best solution in Fig. 2 for each power supply voltage. For the folded-cascode and current-mirror OTAs the circuit areas are not affected by limiting the power consumption as discussed in Sec. 4.3. However, there exists a trade-off between these two metrics for the two-stage OTA.

It is clear that the area rapidly increases when the point where the circuit fails to meet the specification is approached. This is due to the increased transistor widths required to meet the input/output swing. When the upper bound of the transistor widths is reached the specification can no longer be met.

### Impact of scaling the unity-gain frequency

In the sample-and-hold circuit the output from the buffer must settle before the clock arrives. The linear settling-time for the buffer is determined by its first pole. This is approximately the unity-gain frequency of the open-loop amplifier. Hence, the circuit area and power consumption as a function of the unity-gain frequency is of interest.

The possible trade-off between these performance metrics are shown in Fig. 4 for a power supply voltage of 3.3 V. The circuit area has not been constrained. The maximum unity-gain frequency is 360 MHz, 300 MHz, and 260 MHz for the two-stage, folded-cascode, and current-mirror OTA, respectively.

Fig. 4. The power consumption as a function of the unity-gain frequency.

For frequencies below 150 MHz the slew rate specification is limiting the minimum power consumption for the folded-cascode amplifier. Further, the graph shows that each circuit topology has a specific range in which the power consumption is smallest. For all topologies, the power consumption increases rapidly with increased unity-gain frequency.

The circuit areas of each amplifier as a function of the unity-gain frequency is shown in Fig. 5. The power consumption is not constrained. The circuit area is increased for larger unity-gain frequencies.

Fig. 5. The circuit area as a function of the unity-gain frequency for the amplifiers.

### The circuit area vs. power consumption trade-off

The performance measures that usually are to be minimized as long as the specification is met are the circuit area and the power consumption. These measures are associated with the cost of the chip. The area vs. power consumption trade-off, at 3.3 V power supply voltage, is shown in Fig. 6 where the circuits are forced to have a specific power consumption and the objective is to minimize the area. Increasing the power consumption do not necessarily lead to increased design margins, in fact, all circuits used in Fig. 6 have minimum margins. Hence, the number of poor circuit realizations is large.

Fig. 6. The circuit area as a function of the power consumption for the amplifiers.

The circuit area of the two-stage amplifier can be made smaller at the expense of increased power consumption. For the folded-cascode and the current-mirror OTA there are no trade-off between these performance metrics. The points (A-D) in Fig. 6 indicate the best choices of circuit realizations for our application.

In this case the current-mirror OTA is the best topology with respect taken to both area and power consumption. Selecting circuit D instead of A, B, or C will result in a power reduction of 17 %, 31 %, and 33 %, respectively. For the circuit area the savings are 55 %, 47 %, and 35 % for D compared to A, B, and C.

Notice that, the selected circuits are most likely not found using manual design techniques, hence, the savings in area and power consumption can be even larger in that case. Furthermore, since a large number of poor circuit realizations exists, there is a large risk of ending up with an even worse implementation, e.g., the point E, rather than that indicated by the curves in Fig. 6.

### Design example summary

The material presented in the design example is dependent on the performance specification. Hence, no general conclusions about the relations between the circuit topologies can be made. However, the described approach can be used to explore the design space in order to visualize trade-offs and limitations within reasonable time for a set of circuit topologies. Thus, increased design efficiency and circuit performance are obtained.

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